• Xilinx - Senior Verification Engineer - System Verilog/PCI-e Jobs in Hyderabad,India - 23787093

  • Xilinx
  • Save Job
  • 8 - 14 Years
  • Posted : above 1 month

Job Description:






Responsibilities

- Create block level verification plan, test plans and full chip test plan

- Develop block-level test bench and tests in UVM methodology including the scoreboard

- Work on subsystem level verification

- Write C based tests to execute on the processors in the subsystem

- Work with designers to get the coverage closure

- Port the block-level tests to full chip test bench

- Integrate VIPs as needed

- Work with software, validation and emulation teams as needed

- Work on other aspects of verification like CDC, gate simulation

- Work on power-aware verification using UPF

- Assist in the silicon bring up in the lab

- Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology

- Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and function coverage with the design team

- Familiarity in writing System Verilog Assertions

- Good understanding of object-oriented programming concepts

- Prior experience in verifying is system/subsystem level involving multiple SoC blocks

- Prior experience with PCIe Express Transport Layer

- Prior experience in high-speed serial protocols such PCIe and 10G Ethernet

- Prior experience with protocols such as AXI, APB, AHB, ACE etc

- Programming in scripting languages like Python, TCL and Perl

- Excellent communication skills

- Good problem solving skills and analytical ability

- Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc

- Work with cross-functional team such as software drivers, software tools as needed

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 11th Apr 2020

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