• Xilinx - RTL Design & Validation Engineer - Verilog/VHDL Jobs in Hyderabad,India - 23776318

  • Xilinx
  • Save Job
  • 5 - 10 Years
  • Posted : above 1 month

Job Description:

Job Title RTL Design & Validation Engineer

Job Requirements

- Btech/Mtech with 5+ Years of Experience in RTL Design

- Bachelors or Masters in Electrical/Electronics engineering

- Strong academic background

- Strong logic design concepts and computer design

- Expertise in Verilog, VHDL and exposure to industry simulators

- Expertise in front end RTL design flow steps like lint, CDC, STA, etc

- Expertise in IP & System design

Experience in System Validation

Experience with Xilinx Tools & Devices

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 08th Apr 2020

Key Skills:

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