• Wafer Space - Physical Design Engineer - Floor Planning Jobs in Bangalore,India - 25015932

  • Wafer Space
  • Save Job
  • 3 - 18 Years
  • Posted : above 1 month

Job Description:

Able to take up ownership of blocks independently (RTL2GDSII; 28nm and lower technology nodes)

- Interface with RTL designers and solve structural inefficiencies if any

- Functional & DFT Constraint development exposure

- Need to be able to make smart decisions like optimal standard cell selections based on PPA targets

- Need to come up with strategies to control congestion through understanding of specific block level architectural challenges

- Need to come up with strategies to fix RC inefficiencies built into layout and achieve timing closure

- Should be able to construct clocks on multi-clock, synchronous and asynchronous clock domain partitions

- Should be good in STA analysis

- Should have owned DRC/LVS/ANT clean ups at block level

- Implementation experience on IR/IVD/EM analysis & fix

- Should be good in Innovus, Tempus & Genus

- Low Power Implementation experience will be a big plus

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 06th May 2020

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