• Verification Engineer - System Verilog/ARM/UVM Jobs in Bangalore,India

  • Rishyaa Digicorp

Job Description:

1 Develop and integrate subsystems

2 Methodology (OVM/UVM)System Verilog(UVM), Mat lab

3 Xilinix - Altera

4 Tools VCSModel Questa

5 Ip Verification PCI Express,Ethernet,ARM, AHB/AXI, DDR, UART

- Development of verification plan (Vplan)

- Extensive knowledge in VHDL and Verilog

- Extensive Verification knowledge using SystemVerilog/UVM and/or e/Specman

- Good VIP (Verification IP) design knowledge

- Good System Verilog assertions knowledge

- Analysis of Code coverage

- Managing and debugging regressions

- Evaluate regressions and mapping to Vpla

6 Job Title FPGA Design Engineer

Years of Exp 3 - 6 Years

- ASIC/FPGA Designer Profile

- Extensive experience in RTL coding using Verilog,

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 20th Feb 2020

Key Skills:

Company Profile:

Not Mentioned

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