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  • 4 - 10 Years
  • Posted : above 1 month

Job Description:

DFT Engineer

- Experience in DFT especially on Chip level Scan DRC and ATPG

- Should have worked at full chip level

- Knowledge on Synopsys tools is preferred

- Experience in delivering patterns to ATE and support is preferred

- Experience with any of these tools is required

- ATPG - Tetramax, TestKompress

- MBIST - Mentor ETVerify

- Simulation - VCS (preferred), modelsim

- Expertise in test mode timing constraints definition, Hands on experience with prime time is an added advantage

- Expertise in scripting languages such as Perl, shell, etc is an added advantage

- Ability to work in an international team, dynamic environment with good communication skills

- Ability to learn and adapt to new tools, methodologies

- Ability to do multi-tasking & work on several high priority designs in parallel

Experience 5+ years

Educational Qualification - BS/MS EE, EC, or CS

Job Location Bangalore

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 04th May 2020

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