• System Engineer - DFT/ASIC Jobs in Pune,India

  • Amisign Technologies
  • Save Job
  • 4 - 10 Years
  • Posted : above 1 month

Job Description:

JD

- Scan Insertion and ATPG Pattern Generation

- Memory BIST logic generation, implementation and verification

- Scan timing setup and performance verification

- ATPG patterns verification with gate level simulation

- Post Silicon Support to ensure successful bring-up and enhance yield learning

- Understanding of Design For Test methodologies and DFT verification experience (eg scan, memory BIST, JTAG, ? etc)

- Experience with Synopsys TetraMax/DFTMAX, JTAG & Memory Insertion flows or with Mentor TestKompress, JTAG & Memory Insertion flows

- Experience with VCS simulation tools and back annotated simulations

- Experience with PrimeTime static timing tools

- Experience with Perl/Shell scripting, html, and python

Education

- A BSEE/MSEE or equivalent degree and 4+ years of ASIC Design/Test/Verification experience with minimum 4+ years of ASIC DFT experience

Additional Skills

- Diligent, willing to take initiative, and able to handle assignments with minimal supervision

- Demonstrates good analysis and problem-solving skills

- Has an inherent sense of urgency and accountability

- Must have the ability to multi-task in a fast paced environment

- Excellent oral, written, and interpersonal communications skills

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 20th Jan 2020

Key Skills:

Company Profile:

Not Mentioned

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