• Sventl - ASIC Verification Engineer - System Verilog Jobs in Bangalore,India

  • Sventl
  • Save Job
  • 4 - 12 Years
  • Posted : above 1 month

Job Description:

SVENTL INDIA is hiring for ASIC VERIFICATION ENGINEER

Job Role Verification Engineer

- Develop verification environment and tests to perform Functional (RTL) testing at IP level and SoC Level

- Develop IP level/SoC level test plans based on the design/architectural specs

- Coverage Analysis and Coding

- Run simulations & regressions, debug test failures to identify test case issues & RTL design issues

- Define and develop block/full chip level verification environment and its components

Required Skills

- 4 - 9 & above years of experience in ASIC Verification and Methodologies

- Good knowledge of System Verilog, SV-OVM/SV-UVM Methodologies

- Good understanding of RTL concepts

- Good understanding of AHB/AXI protocol

- Expertise in PCI-e/USB/Ethernet/Switch protocol is an added advantage

- Knowledge of Perl/TCL is Must

- Good communication skill

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 15th Mar 2020

Key Skills:

Company Profile:

Not Mentioned

Would you like to try out these free online tutorials?

People who search this job also searched for the following Keywords

Salary trends based on over 1 crore profiles

View Salaries

All rights reserved © 2018 Wisdom IT Services India Pvt. Ltd DMCA.com Protection Status