• Staff Verification Engineer Jobs in Hyderabad,India

  • Xilinx India Technology Services Pvt Ltd
  • Save Job
  • 7 - 10 Years
  • Posted : above 1 month

Job Description:

Job Description Description

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world ARE YOU bold, collaborative, and creative At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable From self-driving cars, to world-record genome processing, to AI and big data, to the worlds first 5G networks, we empower the worlds builders and visionaries whose ideas solve every day problems and enhance peoples lives

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work We are ONEXILINX

Data Center Verification group at New Delhi Site is looking for Senior Design Verification Engineer to provide technical leadership, contribution on FPGA block, sub-system and full chip verification This is a fantastic opportunity for an Engineer with a passion for FPGA or ASIC development to join a growing team with access to world-class components and development infrastructure to work on all aspects of the FPGA development cycle Youll be working in a team responsible for the functional verification of IP components and systems for use by the worlds leading hyperscalers, financial institutions and data science companies

The individual will help design and develop Random Constrained Functional Coverage driven verification environments, at block, sub system and full chip level, to prove the functional correctness of FPGA SoCs

The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on high performance IPs and/or SoC designs Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the FPGA design teams with an eye towards improving overall product quality


Bachelors Degree w/ 7 years or MS w/ 5 years or PhD w/ 1 years in

Electrical/Electronics Engineering, Computer Engineering, or Computer Science

Skill & Experience

Requires proven track record in technical leadership This includes planning, execution, tracking, verification closure and delivery to programs

Requires strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES or Mentor Questa

Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification

Experience in full chip verification is a plus

Requires proficiency in Perl, Python and/or other scripting language

Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus

Experience in modelling C and using C based models in verification is a plus

Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan) is a plus

Debug tests with design engineers to deliver functionally correct design blocks

Identify and write coverage measures for stimulus quality measurements

Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

Packet/wired-networking background, knowledge of Ethernet Layer 2/3,AXI and PCIe is a strong plus

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Software Services, IT-Software
Functional Area : IT Hardware : Hardware Products & Services
Role : Hardware Design
Salary : As per Industry Standards
Deadline : 03rd Mar 2020

Key Skills:

Company Profile:

Xilinx India Technology Services Pvt Ltdarfix

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