• STA Engineer - ASIC/SoC/Synthesis Jobs in Bangalore,India

  • Rishyaa Digicorp

Job Description:

STA / SignOff Timing closure

- ASIC/SoC design & implementation experience with specific background in the areas of synthesis, SignOff STA

- Lower technology nodes like 40nm and below till 14nm/10nm

Key responsibilities

- Includes definition and development of signoff methodology and corresponding implementation solution

- Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs

- Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC

- Streamlining the timing signoff criterions, timing analysis methodologies and flows

- Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow

- Work for Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote teams to address the design challenges in the context of the block, chip, and overall system

- Concepts of CRPR, clock paths analysis and tweaks to meet timing

- Multi Corner and MultiMode analysis

- Close timing at SignOff corners covering the entire modes, delay corners for cells and interconnects

Key Skills

- SOC/Chip level Timing closure and Signoff of high speed complex design with multiple clocks and power domains with minimal supervision

- Expertise in developing and owning Block and full chip Timing Constraints for complex, multi-clock, multi-voltage SoCs

- Expertise in I/O constraints developments for Industry standard protocols would be an advantage

- Good understanding of deep submicron parasitic effects, crosstalk effects, newer statistical timing approaches

- Work with the Implementation team in having the SignOff Timing closure done

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 20th Feb 2020

Key Skills:

Company Profile:

Not Mentioned

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