• St SOC Solutions Physical Design Engineer Timing Closure RTL Synopsys Jobs in Bangalore,India - 23713258

  • Smart SOC Solutions
  • Save Job
  • 3 - 15 Years
  • Posted : above 1 month

Job Description:

JD

- Block Level P&R / Sub-system Level P&R/ Tile Level P&R

- Experienced in Cadence (EDI) or Synopsys (ICC) and Mentor (Calibre) EDA Tools

- Process node experience to be in the range of 40nm & below (ie 28 nm, 16 nm, 10 nm, 7nm)

- Responsible for full chip implementation of complex SoCs (RTL-to-GDSII)

- RTL2GDSII implementation (40/28nm)

- Exposure on Low Power Implementations (multi-Voltage and switchable domains)

- Prior experience handling extremely area and power sensitive designs

- Power Network Analysis and fix exposure a must

- STA-SI analysis and timing closure expertise at block level

- Traditional clock tree synthesis experience

- DRC/LVS/ANT/PERC run and fix expertise

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 29th Mar 2020

Key Skills:

Taking these free online tutorials can help you get your next job

People who search this job also searched for the following Keywords

Sourced**

Salary trends based on over 1 crore profiles

View Salaries

All rights reserved © 2018 Wisdom IT Services India Pvt. Ltd DMCA.com Protection Status