• St SOC Solutions Lead Verification Engineer Verilog UVM Jobs in Bangalore,India

  • Smart SOC Solutions

Job Description:

Job description

1) Strong Verification experience at IP or Subsystem or SOC levels is preferred)

2) Strong in System Verilog/Verilog/UVM

3) Developing Detailed Testplan including Test algorithms from the Spec

4) Identify corner case scenarios for thorough verification

5) Develop Testbench/its components, Test Stimulus & Ability to resolve issues quickly, Offer solutions for automation

6) Strong debugging skills, problem solving skills Identify and address the root cause of bugs

7) Good understanding on assertion based verification and functional and code coverage

8) Solves complex problems with some direction and makes amends to standard methodology or practices

9) Drive collaborative solutions for issues, methodologies and processes related to inter or intra-organization

10) Good attitude & should be a good team player

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 16th Mar 2020

Key Skills:

Company Profile:

Not Mentioned

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