• St SOC Solutions Lead Physical Design Engineer ASIC GDS RTL Jobs in Bangalore,India - 23787293

  • Smart SOC Solutions
  • Save Job
  • 8 - 12 Years
  • Posted : above 1 month

Job Description:

JD

- RTL2GDSII implementation (40/28nm)

- Exposure on Low Power Implementations (multi-Voltage and switchable domains)

- Prior experience handling extremely area and power sensitive designs

- Power Network Analysis and fix exposure a must

- STA-SI analysis and timing closure expertise at block level

- Traditional clock tree synthesis experience

- DRC/LVS/ANT/PERC run and fix expertise

- RF integration exposure a big plus (WiFi, Bluetooth, ZigBee)

- Strong experience on Static Timing Analysis (Primetime), EM/IR-Drop/Cross-talk analysis (PT-SI, Red hawk), formal or Physical Verification (Formality, Calibre)

- Experience in complex SOC integration, Low Power and High Speed Design and Advanced Physical Verification Techniques

- Provide technical guidance, mentoring to physical design engineers

- Interface with front-end ASIC teams to resolve issues

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 11th Apr 2020

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