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  • 8 - 13 Years
  • Posted : above 1 month

Job Description:

What you do at AMD changes everything

At AMD , we push the boundaries of what is possible We believe in changing the world for the better by driving innovation in high - performance computing , graphics , and visualization technologies building blocks for gaming , immersive platforms , and the data center

Developing great technology takes more than talent it takes amazing people who understand collaboration , respect , and who will go the extra mile to achieve unthinkable results It takes people who have the passion and desire to disrupt the status quo , push boundaries , deliver innovation , and change the world If you have this type of passion , we invite you to take a look at the opportunities available to come join our team

The candidate will be responsible for implementing the place and route of design blocks including floorplanning , placement , clock tree building , routing , timing optimizations , DRC , LVS fixing , IR drop analysis , Formal verification , power intent checks etc The candidate will also be responsible for block level physical design closure in terms of timing , power , DRC / LVS etc


At least 8+ years experience in complex ASIC Design projects

Have in depth knowledge of entire physical design process from floorplan till GDS generation

Good Exposure to Physical Verification Process

Have hands - on experience in latest sub - micron technologies below 20nm

Hands on experience in leading PnR tools Synopsys ICC / Cadence Encounter etc

Experience in low power designs and handling congestion or timing critical tiles will be preferred

Should be a quick learner and have good attention to detail

Experience in ECO implementation preferred

Scripting skills in Perl / Python etc

Must have good communication & problem - solving skills

Should be able to handle PnR tasks with minimal supervision

Bachelor / Master Degree in Electronics Engineering

Desired Skills

1 SoC implementation expertise Multimillion gates integration

2 Physical Synthesis , Constraints validation

3 Floorplanning , Power planning

4 Clock Tree Synthesis (CTS)

5 Scan Synthesis , Scan re - order

6 Static Timing analysis (STA)

7 Analysis IR , EM , Noise

8 Physical Verification

#LI - SK2

Requisition Number Job Function Design Find similar jobs

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Profile Summary:

Employment Type : Full Time
Industry : Recruitment Services
Salary : Not Disclosed
Deadline : 31st Mar 2020

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