• Senior Staff ASIC Engineer / Staff Jobs in China - 24977382

  • Qualcomm Inc
  • China

Job Description:

Job Overview Qualcomm Global SOC engineering organization has several exciting openings for several motivated individuals to lead the IP sharing initiative with our Joint Venture partners The qualified individuals will work directly with the internal teams to deliver advanced technology IPs Main areas of Responsibilities Provide technology IP integration support to QC JV partners throughout their SOC development Liaison between Qualcomm engineering teams, 3rd party vendors, and JV engineering teams to architect, integrate and validate the design that meets the partners acceptance criteria Maintains regular communication with key stakeholders to ensure continued alignment between team deliverables and product execution plan Prepare engineering collaterals from Qualcomm IP engineering teams, include externalization of docs, simulation models, test benches, test patterns, design databases, and supporting tools, utilities and scripts Use EDA tools to validate the package content where necessary Deliver the engineering collaterals thru approved systems Assist partners in IP integration Use deductive and inductive problem solving approach, debug functional models and functional vectors related to complex customer test cases including but not limited to power sequencing, concurrency, memory contention, and system throughput Create an emulation environment for JV partners to validate the combined system SOC Assist partners in physical implementation Align design metrics between the IP and the SOC (corners, views, process POR etc) Facilitate exchanges between Qualcomm engineering, JV partners, foundry design services and 3rd Party IP vendors Optimize JV SOC floorplan using various Qualcomm IP layout Resolve boundary issues including timing and LVS/DRC Assist partners in productization Provide onsite bring up support related to Qualcomm technology IP Act as a principle lead representing Qualcomm engineering team, effectively utilizes advanced problem solving and SOC engineering practices to resolve complex architecture, design, or verification problems Extensive system debug experience is required

Minimum Qualifications Bachelors degree in Science, Engineering, or related field
7 years ASIC design, verification, or related work experience

Preferred Qualifications Minimum qualification includes 7 to 12 years of SOC design experience in Logic Design, VHDL, Verilog & SV (SystemVerilog) RTL, verification/emulation, synthesis, LINT and static timing analysis, clock domain crossing techniques/implementation Strong understanding of chip integration methodologies & flows Solid background in scripting for automation of design methodologies & flows is desired Detail oriented with strong organizational, exceptional problem solving, and great communication skills (both written and oral) Fluent in English and Mandarin is a must Ability to work in a highly collaborative fast-paced team environment is required Strong mobile knowledge is highly desired

Education Requirements BSc, electrical engineering is required
MSc, electrical engineering is desired

Keywords

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : IT-Hardware/Networking, Telecom
Functional Area : IT Hardware : Hardware Products & Services
Role : Hardware Design
Salary : As per Industry Standards
Deadline : 06th May 2020

Key Skills:

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