• Senior Designer - Physical Implementation - VHDL/Verilog/Synopsys Jobs in Noida,India - 24996275

  • Infinity HR

Job Description:

Role Purpose

- The Physical Implementation Senior Designer covers all the steps in the back-end digital design flow from Netlist to Tape-out, for complex ASIC/SoC designed using leading edge SOI/FinFET technologies (28nm,16nm/14nm,7nm)

Detailed Responsibilities description

- Pad Ring Definition / Pin assignment, Floorplanning and Block Placement

- Cell Placement, Clock Tree Synthesis, Routing

- Full chip assembly and integration

- Layout Extraction, Back Annotation and Delay Calculation

- Layout Verification (DRC/LVS/DFM), EM checking, Power Analysis

- Timing Closure at subchip and full-chip level - ECO timing loops

- Chip Finishing (FEOL tiles / BEOL tile / Embedded metrology)


Must have skills

- Verilog/VHDL basic language

- Knowledge on CAD tools for ASIC layout design, verification, floorplanning and timing analysis from vendors such as Synopsys, Cadence, Mentor Graphics are a must for this position

- Cadence Innovus, Synopsys ICC2

- Mentor Calibre

- Synopsys Design Compiler, Synopsys PrimeTime, Synopsys Formality

- Cadence Tempus

- Linux operating system, cshell and tcl language

Good to have skills Basic knowledge on DFT tools as following ones Synopsys Test Compiler, Synopsys DFT Compiler, Synopsys Tetramax

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 06th May 2020

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