• RTL Design Jobs in Hyderabad,India

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  • 2 - 5 Years
  • Posted : above 1 month

Job Description:

RTL Design

2 - 7 Years

Bengaluru, Hyderabad

Job Description

Xilinx Hyderabad is looking for a self-motivated engineer to work on creation of designs and timing closure for FPGAs We are looking for smart, creative people who have a passion for solving complex problems
The ideal candidate should have a strong background in RTL design using Verilog/VHDL and should have worked on FPGA software tools like Vivado and Quartus with strong foundations in timing analysis & digital design The candidate should have a solid understanding of timing constraints, RTL coding styles and applications The candidate will be responsible for creating complex designs

Create designs for Xilinx architectures and also on few other FPGA architectures and compare performance

BS or MS in EE or CE with 2 years of experience in digital design and/or timing closure
Strong background in RTL design using Verilog/VHDL
Timing Constraints (SDC) & Static Timing Analysis
Strong understanding and usage of ASIC and/or FPGA software tool chain like Vivado or Quartus
Strong Digital Design Fundamentals and applications
TCL Scripting language
Applications and Designs in Wireless/Wired domain

PreferredExposure to any of these areas

Scripting language like perl or python

Salary Not Disclosed by Recruiter

IndustrySemiconductors / Electronics

Functional AreaIT Software - Embedded, EDA, VLSI, ASIC, Chip Design

Role CategoryProgramming & Design

RoleTeam Lead/Technical Lead


VHDL Timing Analysis FPGA Timing Closure Verilog Xilinx RTL Design

Desired Candidate Profile

Please refer to the Job description above

Company Profile

Cambio Consulting India Pvt Ltd


Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Others - other Industry
Functional Area : IT Hardware : Hardware Products & Services
Role : Hardware Design
Salary : As per Industry Standards
Deadline : 10th Mar 2020

Key Skills:

Company Profile:


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