• Principle Design Implementation Engineer Jobs in Malaysia - 23778366

  • Microchip Technology India Pvt Ltd
  • Malaysia
  • Save Job
  • 5 - 10 Years
  • Posted : above 1 month

Job Description:

Job Attributes Job Id 9159

Req Id I639-19A-D

Category Engineering

Job Type Full-time

Education Level Bachelors Degree

Job Level Executive

Hires Needed 4

Job Location Penang, Penang

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Principle Design Implementation Engineer
Penang, Penang

Company Description Microchip Technology Inc is a leading provider of embedded control applications Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM) We also license Flash-IP solutions that are incorporated in a broad range of products



Microsemi, a subsidiary of Microchip offers a comprehensive portfolio of semiconductor and system solutions for data center, communications, aerospace and defense, and industrial markets Microsemis Advanced Engineering Services central team (AES) offers industry leading digital and mixed-signal design implementation of full RTL2GDS spectrum on advanced technology nodes with cutting edge EDA tooling platform

As a Design Implementation engineer, the candidate will be supervised by a local manager, be engaged into projects to perform the synthesis, DFT implementation, timing closure and ensure the design is implemented correctly with various checks/verification/audit Also, be involved in design flow/methodology definition and development to ensure the design team is always using best-in-class design methodology

Responsibilities

Own macro level and potentially system level functional modules and implement the macros to high quality standard
Implement plans to synthesize, implement Design-For-Test (DFT) and close timing on complex digital integrated circuits at the block, subsystem or device level (100K to 10M gates) which are coded in VHDL/Verilog
Work with various design groups across different disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements
Design, implement and maintain synthesis, DFT, Place & Route (APR) and Static Timing Analysis scripts using best-in-class methodologies
Analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones
Communicate regularly with the project teams world-wide to resolve issues and to ensure meeting targeted goals and schedule
Provide/propose new/enhance synthesis, DFT and STA flow and methodology to reduce the development TAT to meet product requirements

Job Requirements

Qualifications

This position requires at least BSEE with 5-10 years of ASIC development experience in a fast paced environment You are required to have expertise in a wide range of areas in design implementation, tools and flows

BEng/MEng in EE or Computer Science with the completion of several complex ASIC or IC tapeouts in VDSM process technology nodes
Design and Synthesis experience in high performance design (high speed / low power) is a must State of the art knowledge of semi-custom design & implementation tools
Experienced with tools and methodologies for Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization and Logic Equivalency Check
Experience in synthesis algorithms, best RTL coding for synthesis, low-power and high-speed design trade-offs, physical aware synthesis, deep sub-micron process effects
Understand Design-For-Test tools (Tetramax, DFT Advisor) & methodologies (Scan chains, ATPG, BIST, Fault models, Fault Coverage and generation)
Understand JTAG IEEE standard for board level connections testing and/or enable block level DFT testing is a plus
Experienced in Static Timing Analysis tools/flows (eg Prime Time, Tempus or equivalent) and constraint checkers
Experienced in auto Place & Route (APR) tools/flows (eg ICC/ICC2, Innovus or equivalent)
Good scripting skills in Perl, TCL and Shell, particularly in synthesis & timing algorithms, with solid understanding of UNIX/LINUX
Working knowledge of RTL coding
Low power methodologies and impact on overall design goals
Able to work autonomously as well as in a team environment across multiple geographical sites, with a strong desire to succeed
Excellent debugging, problem solving and analytical skills
Excellent verbal and written communication skills Strong interpersonal skills
Have lead and mentor others and work under challenging environment

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Telecom, IT-Hardware/Networking
Functional Area : IT Software : Software Products & Services
Role : Software Engineer
Salary : As per Industry Standards
Deadline : 07th Apr 2020

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