• United States Of America, Usa
  • Save Job
  • 5 - 7 Years
  • Posted : above 1 month

Job Description:

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology Position Description These support roles include the following operations and requirements
o Superior skills at understanding customer needs and identifying solutions to their challenges with Cadence signoff tools (Tempus)
o Proven design knowledge and experience in applying solutions in the static timing analysis and power analysis space
o Demonstrated ability in customer tool debug and usage issues (on-site and remote)
o Working knowledge of parasitic networks and modeling of capacitance, resistance and inductance
o Experience and in-depth familiarity with usage and development of timing libraries, design constraints, static timing analysis and underlying timing calculations
o Past direct experience with Synopsys STA products, or other equivalent products
o Direct expertise in applying power analysis, static timing and parasitic extraction products and techniques to advanced Low Power designs incorporating multiple power domains and multiple supply voltages
o Outstanding oral communication skills to deliver customer and marketing presentations, product updates, etc
o Close collaboration with R&D on issues using established protocols (CCRs/SRs)
o Communicate with customers on issue workarounds and new tool fixes
o Mentor and lead less-experienced team members
o Participate in customer benchmark activities and pre-release code bashing with DSG products
o Must be motivated to mentor (and be mentored) by colleagues to increase team productivity
o On-site customer office hours, when local, is a MUST-HAVE
Position Requirements
The candidate will have broad knowledge and at least 2-5 years of experience in the physical design process of modern SOCs (45nm or below) Demonstrated hands-on experience in the RTL-to-GDS process for complex processors, IP or SOCs is required The candidate will possess a self-starter mindset with an established track record of complex problem solving in SOC physical design The candidate should possess excellent communication skills and be adept at working with both customer engineers/mgmt as well as Cadence team members
The candidate must have demonstrated expertise in several of the following areas is required
o Static timing analysis
o Timing optimization
o Power Analysis (Static, Dynamic, Leakage, EM)
o Extraction
o RTL Synthesis/Physical Synthesis
o Design constraint creation
o Floorplanning/Power Grid Design
o Low power implementation
o Clock Tree Synthesis
o Routing
o Physical Verification
o CAD flow debug/optimization
The candidate must have proficient software skills in the automation of physical design software including several of the following TCL, PERL, CSH, BASH, AWK, SED, or SKILL Minimum BSEE/MSEE plus 5 to 7 years experience

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Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : Telecom, IT-Hardware/Networking
Functional Area : IT Software : Software Products & Services
Role : Software Engineer
Salary : As per Industry Standards
Deadline : 19th Jan 2020

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