Job Description:

Job Overview The responsibility includes

  • Independent planning and execution of RTL-to-GDSII Full exposure to all aspects of design flows like, synthesis, floor-planning, placement, CTS, routing, crosstalk avoidance, physical verification

  • Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence

  • Well versed with parasitic extraction, LVS/DRC and other Physical verification checks, IR/EM analysis

  • Minimum Qualifications

  • Experience in Physical Design Execution

  • Should have good exposure to high frequency design convergence and descent exposure to physical design methodology

  • Masters/bachelors degree in electrical/Electronics science engineering with at least 5 years of experience in IC design

  • Experience in leading block level or chip level Timing closure & Physical Design activities

  • Work independently in the areas of RTL to GDSII implementation

  • Ability to collaborate and resolve issues wrt Physical design, constraints validation, verification, STA, IR/EM analysis etc

  • Knowledge of low power flow (power gating, multi-Vt flow, power supply management etc)

  • Circuit level comprehension of time critical paths in the design

  • Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc)

  • Strong problem-solving skills

  • Good communication and technical writing skills, along with proven ability to collaborate with Physical design teams across multiple sites

  • Tcl/Perl scripting Willing to handle technical deliveries with a small team of engineers


Profile Summary:

Employment Type : Full Time
Industry : Consumer Durables / Electronics
Salary : Not Disclosed
Deadline : 13th Apr 2020

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