• Memory Layout design Engineer Jobs in Bangalore,India - 24843436

  • Qualcomm Inc
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  • 0 - 3 Years
  • Posted : above 1 month

Job Description:

Company Qualcomm Technologies, Inc

Job Area Engineering - Hardware

Location India - Bangalore

Job Overview Experience in Memory Layout design Leafcell layout design from scratch till top level integration Good knowledge on different types of memory architecture Good knowledge in optimized layout design for better performance Minimum Qualification Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions and Softcheck Proficient in Cadence Virtuoso layout editor and Mentor Graphics CalibreRVE for PV checks Required Qualification Knowledge in Finfet technology, layout design and DRC limitations

Minimum Qualifications Bachelors degree
3 Plus years experience

Preferred Qualifications Experience in Memory Layout design Leafcell layout design from scratch till top level integration Good knowledge on different types of memory architecture Good knowledge in optimized layout design for better performance Minimum Qualification Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions and Softcheck Proficient in Cadence Virtuoso layout editor and Mentor Graphics CalibreRVE for PV checks Required Qualification Knowledge in Finfet technology, layout design and DRC limitations

Education Requirements Bachelors/Masters in Electrical Engineering

Keywords STDCELL, Characterization

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : IT-Hardware/Networking, Telecom
Functional Area : IT Hardware : Hardware Products & Services
Role : Hardware Design
Salary : As per Industry Standards
Deadline : 03rd May 2020

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