• Low Power Design / Methodology Engineer Jobs in United States Of America - 23858093

  • Qualcomm Inc
  • United States Of America, Usa

Job Description:

Job Overview Design low power / power management controller IP blocks including AVS (adaptive voltage scaling), ACD (adaptive clock distribution), LMH (limit management hardening), on-chip sensor controller and digital power meter
Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification for IP blocks
Work closely with technology/circuit design team to close IP block specification/requirement
Work closely with verification/physical design team to complete the IP design implementation
Support SoC team to integrate low power / power management IP solution into wireless SoC chips and front-end design flows
Work closely with system/software/test team to enable the low power feature in wireless SoC product
Evaluate new low-power technologies and analyze their applications to address requirements
Provide feedback for low-power chip and system architecture
Understand and perform block & chip-level power analysis
Understand and create block-level power models

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company

Minimum Qualifications Bachelors degree in Science, Engineering, or related field

2 years ASIC design, verification, or related work experience

Preferred Qualifications 3 years of experience doing low power digital ASIC design Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding, simulation, synthesis, STA
Understanding of electrical engineering concepts, circuit analysis and logic design skills
Previous experience in AVS (adaptive voltage scaling) desired
Familiarity with advanced low power techniques and high speed clocking desired
Proficiency in Verilog/System Verilog coding, verification techniques, and scripting language, such as Perl, Python, Tcl, and Make etc
Good understanding of SoC architecture/micro-architecture
Strong debugging capabilities at simulation, emulation, and Silicon environments, including ability to design interesting debug experiments
Collaborate closely with cross-function team to research, design and implement performance and power management strategy for product roadmap

Education Requirements Masters or PhD in Electrical or Computer Engineering

Keywords Low power design, Power Management, UPF, CPF, Adaptive Voltage Scaling, methodology, power estimation

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : IT-Hardware/Networking, Telecom
Functional Area : IT Hardware : Hardware Products & Services
Role : Hardware Design
Salary : As per Industry Standards
Deadline : 19th Apr 2020

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