Job Description:

Bangalore- MTS- ASIC- Layout- Design- Engineer MTS ASIC/ Layout Design Engineer Search jobs by keyword Search jobs by location MTS ASIC/ Layout Design Engineer Advanced Micro Devices Apply for Job Enter your email to apply What you do at AMD changes everything

At AMD, we push the boundaries of what is possible We believe in changing the world for the better by driving innovation in high- performance computing, graphics, and visualization technologies building blocks for gaming, immersive platforms, and the data center

Developing great technology takes more than talent it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world If you have this type of passion, we invite you to take a look at the opportunities available to come join our team


Understand the architecture of the graphics IP and functional block being designed

Build C/ C++ model for simulation

Build test bench and monitors for DUT

Compose test plan and validation vectors to ensure functional completeness

Debug function/ performance bugs of graphics IP

Work with global Front- End design team and physical design team for large scale ASIC chip physical implementation

Focus on physical design of deep sub- micron GPU chips including block level (full chip) floor planning, timing closure, place&route;, physical verification etc


Have in depth knowledge of entire design process from Design specification, defining architecture, micro- architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape- out, and post- Si debug

Have hands- on experience in Chiplevel Design/ Integration activities

Some Physical Design exposure required

Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc

Some exposure to DFT is a strong plus

Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD placement, etc

Should have expertise in Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC Good knowledge of datapath compilers is required

Expertise in Perl and Tcl is a must

Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus

Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites

Must have good communication & Analytical thinking skills

Should have proficiency in flow development and scripting

Should be able to Lead a team, and provide Technical mentoring and guidance to junior engineers

Master with at least 5 years or Bachelor with at least 8 years working experience in ASIC area Job Function Design Find similar jobs

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Profile Summary:

Employment Type : Full Time
Salary : Not Disclosed
Deadline : 18th Mar 2020

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Company Profile:

Advanced Micro Devices, Inc
Advanced Micro Devices, Inc

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