• InSemi Technology - Memory Layout Engineer - Physical Verification Jobs in Bangalore,India - 24922455

  • Insemi Tech
  • Save Job
  • 2 - 7 Years
  • Posted : above 1 month

Job Description:

Greetings from Insemi Technology (wwwinsemitechcom)

We have an excellent opportunity for Memory Layout for Bangalore location If you are interested in exploring this opportunity please share your profile

- 2-7 years of experience

- Memory Layout Design Engineer

- Candidate must have experience in layout design of memory leaf cells and at top level of memories

- Candidate should have worked on 65nm / 45nm / 28nm /16nm/ 7nm and lower process technologies and have understanding of issues like WPE (Well Proximity Effects), LOD (Length of Diffusion) effects

- Experience in lower node below 28nm and on FinFET or FDSOI will be favourable

- Candidate must have good understanding of physical verification checks DRC, LVS, ERC and reliability checks IR and EM; must have worked on cadence Virtuoso for layout design and Calibre for physical verification checks;

- Candidate must have good understanding of basics of CMOS circuits; basic knowledge of skill is required

- Candidate must have good communication skills, both verbal and oral

- Advanced Skill to develop layout and schematic tiler would be very valuable Perl scripting expertise would be good to have

Appreciate if profile share with the below details

Current CTC

Expected CTC

Notice Period (Should not exceed 30 days)

Current Location

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 05th May 2020

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