• FPGA Design Engineer - ASIC/RTL/System Verilog Jobs in Bangalore,India

  • Rishyaa Digicorp

Job Description:

ASIC/FPGA Designer Profile

- Extensive experience in RTL coding using Verilog, System Verilog and VHDL

- Extensive domain knowledge

- Switching,

- Signal processing,

- High speed serial I/F

- RTL simulations and debugging

- Implementation of test cases for verification

- Experience from Logic synthesis

- Expertise in Verilog Hardware Description Language

- Good fundamentals of logic design and RTL coding

- Experience in synthesis and timing closure

- Individual ownership of standalone FPGA designs

- Support for HW board bring-up

- Working knowledge of lab equipment such as oscilloscopes and logic analyzers

Desired experience

- Knowledge of scripting languages

- Working knowledge of 1000/100/10M Ethernet

- Experience designing FPGAs with embedded soft or hard processors

- FPGA implementation of closed loop control systems

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 20th Feb 2020

Key Skills:

Company Profile:

Not Mentioned

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