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  • 4 - 14 Years
  • Posted : above 1 month

Job Description:

Design Verification Engineer


- BE/BTech/BS or MS/MTech in EE or CE with 6+ years of work experience

- Hands on experience with verification of System Verilog designs and usage of simulation tools/debug environments such as Synopsys VCS, Verdi tools

- Strong understanding of state of the art verification techniques

- Expertise in shell/PERL and other scripting tools

- Excellent problem solving skills and willingness to think outside the box

- Excellent communication skills and experience working with global teams


- Experience as a verification engineer

- Understanding of various verification methodologies, tools and infrastructure for high performance IP and/or VLSI designs

- Exposure to FPGAs, FPGA programming, and FPGA software tool chain

Profile Summary:

Employment Type : Full Time
Salary : Not Mentioned
Deadline : 07th Jan 2020

Key Skills:

Company Profile:

Not Mentioned

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