• Design-Technology-Co-Optimization Jobs in United States Of America

  • Qualcomm Inc
  • United States Of America, Usa

Job Description:

Job Overview Lead, influence and advocate design teams and foundry suppliers to adopt design-to-yield, design-for-durability guidelines and work flows harnessing expertise and experience from design-technology-co-optimization(DTCO) methodologies with digital design teams all the way to place-and-route flows, design rule (DR) creation/management/application methods and semiconductor technology development-to-production experience in advanced sub-10nm semiconductor fabrication facilities

All Qualcomm employees are expected to actively support diversity on their teams, and in the Company

Minimum Qualifications * Bachelors degree in Engineering, Information Systems, Computer Science, or related field

* 5 years Hardware Engineering experience or related work experience

Preferred Qualifications 5 years DTCO/DR/DFM experience in sub-10nm CMOS commercial technologies or equivalent Prefer 5 years in a semiconductor technology development team inside a silicon fabrication facility in either of these capacities * Lithography, etch, CMP process integration engineer * CMOS process integration engineer responsible for qualification of CMOS technologies from development to production * Yield enhancement and/or yield improvement engineer responsible for identifying yield issue process or design root cause and solving them * DR or design-for-manufacturing (DFM) engineer responsible for creation, maintenance and application of design rules to users * DTCO fab engineer for foundry standard cells (STDCELL) crafting initial technology definition DR to optimize Power-Performance-Area (PPA) metrics when STDCELLs are synthesized in a typical digital CPU block, including but not limited to Place-and-Route efficiency metrics, IR drop minimization and metal electromigration reliability requirements * Process test structure design and layout engineer who understands all of the above and implements relevant test keys to enable characterization of various critical effects that lead back to updated DR and DTCO guidelines Able to evaluate the process risk impact of new finfet design rules to IP/SOC designs concurrently with foundries and design teams Generate viable execution work flows to mitigate design impact and/or turn them into distinct design use features in partnership with enablement teams Ability to craft and author in-house restricted design rules (RDR) that capture unique Qualcomm lessons learnt and BKM to enable competitive advantage in Qualcomm designs in the communications chips marketplace Require self-motivated individual with at least 2 years design team interaction experience including but not limited to, IP, SOC, Physical Design, Place-and-Route space Knowledgeable in layout dependent and parasitic effects Multi-patterning, finfet technology familiarity required Knowledge of analog sensitive/critical circuits (matching, symmetry, parasitic IR drop identification), especially any unique finfet matching methods non-obvious to general public user Prior experience in planer CMOS technology and 16nm ~ 11nm finfet design rules and ability to respond effectively to production maturity design team DR questions also highly desirable Experience with foundry Cadence tech file, map file setup, ability to use foundry supplied verification decks using Calibre Interactive highly desirable

Education Requirements Required Bachelors, Electrical Engineering or equivalent experience
Preferred Masters, Electrical Engineering or equivalent experience

Keywords DTCO, DR, DFM

Profile Summary:

Employment Type : Full Time
Eligibility : Any Graduate
Industry : IT-Hardware/Networking, Telecom
Functional Area : Production/Manufacturing/Maintenance/Packaging
Role : Design Engineering
Salary : As per Industry Standards
Deadline : 08th Apr 2020

Key Skills:

Company Profile:

Qualcomm Inc



Company Turnover
10000 10000+ Crores

Company Size
10001 10001+ Employees

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